Computer for simultaneous computation of a reference signal and an information signal until reference signal reaches a predetermined value



United States Patent Inventor Alvin Vachitis Englishtown, NJ. Appl. No.619,710 Filed Mar. 1, 1967 Patented Dec. 22, 1970 Assignee DranetzEngineering Laboratories,

Incorporated Plainfleld, NJ. a corporation of New Jersey COMPUTER FORSIMULTANEOUS COMPUTATION OF A REFERENCE SIGNAL AND AN INFORMATION SIGNALUNTIL REFERENCE SIGNAL REACHES A PREDETERMINED VALUE PrimaryExaminer-Eugene G. Botz Assistant Examiner-Joseph F. RuggieroAttorney-Wallenstein, Spangenberg, l-lattis & Strampel ABSTRACT: Acomputer utilizing a reference signal and an information signal whereinsaid signals are simultaneously computed (such as division and/ormultiplication, or time integration) until the computed reference signalreaches a predetermined value, whereby the computed reference signalindicates the desired computation of the information signal. Where thecomputation is a time integration over a time interval, the timeinterval is determined by the time integrated reference signal reachinga predetermined voltage value corresponding to the end of the timeinterval, and the time integrated information signal indicates the timeintegral of the information signal regardless of variations in thereference signal and the related information signal. Where the referenceand information signals are cyclic wave signals, the integration of saidsignals is begun at the start of a half-cycle (preferably the firsthalf-cycle) of the reference signal, is continued until the timeintegrated reference signal reaches at least said predetermined value,and then at the start of an ensuing halfcycle (preferably the next firsthalf-cycle) of the reference signal, the integration is stopped and theintegrated reference and information signals are partially dischargeduntil the time integrated reference signal returns to said predeterminedvalue, whereby the time integrated information signal indicates the timeintegral of the information signal for an integral number of half-cyclesor full cycles over the time interval.

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coivrru'rsn FOR SIMULTANEOIIS CONWUTATION or A ssrsnsncs SIGNAL AND AN-i TION SIGNAL UNTIL REFERENCE SIGNAL 2 C PREIDETERMII it VALUEBACKGROUND OF INVENTION 'ageiproducing the signals and, also, wherecyclic wave signals are integrated, due to failure to integrate integralnumbers of half-cycles or full cycles of said cyclic wave signals.

SUMMARY 0s THE INVENTION In accordance with this invention, theaforementioned deficiencies and inaccuracies are eliminatedl Here, inaccordance with one aspect of this invention, .a' reference signal and arelated information signal are providedjand computations or integrationswith respect to time of bothof these signals are simultaneouslycontinued until thecomputed or integrated reference signal reaches apredetermined'value. Then, the computations or integrations aresimultaneously stopped and thecomputed or time integrated'informationsignal indicates the computation or time integral of the informationsignal. Unwanted variations in the voltage providing the reference andinformation signals are completely compensated for, the time intervalbeing shortened upon increases in voltage and being lengthened upondecreases in voltage, with the result that accurate computations orintegrations for the time inter valare assured.

Where the reference and information signals are cyclic Wave signals, asfor example, AC signals or the like, they are processed, as for example,by inverting the second half-cycles to provide processed reference andinformation signals which are integrated with respect to time. Here, inaccordance with a further aspect of this invention, the simultaneousintegrations I of the processed signals are begun at'the start of ahalf-cycle (preferably the first half-cycle) of the reference cyclicwave signal, are continued until the computed or time integratedreference signal reaches at least said predetermined value, and then, atthe start of an ensuing half-cycle (preferably the next fustwhalf-cycle)of the reference cyclic wave signal, the computa'tions or integrationsare simultaneously stopped and the computed or integrated reference andinformation signals are partially discharged or decreased until thecomputed or integrated reference signal returns to said predeterminedvalue. The computed or time integrated information signalthereuponindicates the computation or time integral of the informa tioricyclic wave signal for an integral number of half-cycles or full cyclesover the time interval, thus avoiding inaccuracies which would be causedby asymmetric integration of the cyclic wave signals, the resultantoutput being the voltage ratio at the average values of the cyclicsignals.

One principal object of this invention resides in the computing methodand another principal object of this invention resides in an apparatusfor performing the computing method.

Some significant advantages of the computing method and the computer ofthis invention over other methods and apparatus for obtaining similarfunctions are as follows. The computation can be performed upon as fewas one cycle of information. The input signals may be continuous wave orgated wave trains. With an external trigger or timing signal, thecomputation can be performed at any desired time after the signal sourceis turned on. Computations or integrations are always performed for timeintervals which preferably are an integral multiple of cycles of theinput signals and which are then normalized to a value that would haveresulted in the designed time interval. F ullwave synchronous detectionreduces the errors resulting from second harmonic distortion of thesignal inputs and provides the means for trigonometric computations.After the computation has been performed, the output signal may be pureDC. The output signal may be held at its value for a long period of timedependent only upon the quality of the integrators, namely, the qualityof the integrating capacitors and operational amplifiers. An externallycontrolled DC signal may be applied to perform additional multiplicationor division simultaneously with the computation. Any number ofadditional computing elements (with control circuitry) may be added tothe basic unit so that all related computations can be accomplishedsimultaneously. After the output has been measured, the comparatorvoltage input may then be varied to perform additional computations.

Other objects of this invention residein the combination of computingsteps. and in the combination of elements forming the computer, and inthe cooperative relationships therebetween. I

Further objects and advantages of this invention will become apparent tothose skilled in the art upon reference to the accompanyingspecification, claims and drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified schematic wiringdiagram generally illustrating the construction and the manner ofoperation of the preferred form of the computer of this invention forproviding integrations over a time interval;

FIG. 2 is a chart generally illustrating the control and integration ofthe reference and the information signals;

FIG. 3 is a schematic diagram of a sinusoidal AC system for producingreference and information signals with respect to an impedance devicewherein the signals may be computed by the computer illustrated in FIGS.8A and 8B;

FIG. 4 is a schematic wiring diagram similar to FIG. 3 and illustratingdifferent connections to be made to the computer; i

FIG. 5 is a schematic diagram of a system for producing reference andinformation signals in connection witha device under test and it alsomay be utilized in connection with the computer of FIGS. 8A and 8B FIG.6 is a schematic diagram for testing acoustical devices or the like andfor producing. reference and information signals to be computed by thecomputer of FIGS. 8A and 8B;

. FIG. 7 is a schematic diagram of another circuit for producingreference and information signals in connection with a device under testwherein the sine wave signals have high distortion and/or high harmoniccomponents;

FIGS. 8A and 8B constitute a block diagram of the preferred form of thecomputer of this invention;

FIG. 9 is a series of curves illustrating the various signals present inthe reference channel of the computer of FIGS. 8A and 813 under certainoperating conditions;

FIG. 10 is a series of curvesoccuring in the information channel of thecomputer wherein the computer is arranged for computing the seriesresistance component of the impedance of FIG. 3;

FIG. 11 is a series of curves occuring in the information channel of thecomputer for computing the series reactance component of the impedanceof F IG. 3;

FIG. 12 is a series of curves occuring in the information channel of thecomputer for computing the magnitude of the impedance of FIG. 3;

FIG. 13 is a series of curves appearing in the information channel ofthe computer for computing the power factor with respect to theimpedance of FIG. 3;"

FIG. M is a series of curves appearing in the reference DESCRIPTION OFTHE PREFERREDEMBODIMENTS For a general understanding of this invention,reference is made first to the simplified schematic wiring diagram ofFIG. I for providing time integrations over a time interval. Here, asource of voltage is applied to a terminal 50 of a network includingseries resistances R5 and R6 connected to ground and series resistancesR7 and R8 connected to ground. The resistance R8 represents theresistance of an electrical device under test. For 1 percent accuracy ofmeasurement of resistance R8, the resistance R7 should be at least 100times larger than resistance R8. It is desirable that the ratio ofresistance R6 to resistance R5 be equal to the ratio of resistance R7 tothe maximum value of resistance R8. The juncture of resistances R5 andR6 provides an information signal E1 which is proportional to theapplied voltage, and the juncture of the resistances R7 and R8 providesan information signal E2 which is determined by the value of the:resistance R8 of the device under test. In accordance with' one-aspectof this invention the reference signal E1 and the information signal E2are simultaneously integrated over a desired predetermined timeinterval. The resistance R6 is so selected or adjusted that under idealvoltage conditions the integration of the reference signal E1 to apredetermined value will occur in said desired predetermined timeinterval. The resistance R6 is so selected or adjusted that under idealvoltageconditions the integration of the reference signal E1 to apredetermined value will occur in said desired predetermined timeinterval. The reference signal E1 is routed through a reference'channelincluding an integrator which may comprise a resistance RI, a capacitorC1 and an operational amplifier for producing an integrated referencesignal E14. The information signal E2 is routed through an informationchannel including an integrator which may comprisea resistance R3, acapacitor C2 and an operational amplifier 16 for producing an integratedinformation signal E38. The reference channel integrator and theinformation channel integrator have the same integrating characteristicsand in this respect the resistance values of R1 and R3 are the same, thecapacitance values of the capacitors Cl and C2 are the same and theamplifying characteristics of the operational amplifiers 15 and'16 arethe same.

The computer also includes avoltage comparator 35, labeled VOLT COMP, towhich is supplied a DC comparator voltage signal input E from a terminalB. The computer further includes a pair of switches SW7 and SW15 forcontrolling the simultaneous application of the reference signal E1 andthe infonnation signal E2 to their respective integrators. The referencechannel integratorand the information channel integrator are providedwith switches SW8 and SW16 which are for the purpose of simultaneouslycompletely discharging the integrators when they are closed. Thereference channel integrator and the information channel integrator arealso respectively provided with a discharge circuit including resistanceR2 and switch SW9 and a discharge circuit including resistance R4 andswitch'SW17 for simultaneously partially discharging the integratorswhen the switches SW9 and SW17 are closed, the resistances R2 and R4being equal. The operations of the switches SW7, SW15, SW3, SW16, SW9and SW17 are controlled by control circuits schematically illustrated indotted lines in FIG. 1 in response to a signal pulse E3 and the voltagecomparator 35. The value of the resistance R6 is such that the referencesignal E1 is integrated to an integrated reference signal value E14which is equal to the reference voltage value E25 within the desiredpredetermined time interval. In other words, if there were no unwantedvariations in the voltage applied to the terminal 50 the iarlrtegrationwould take place precisely within the time interv When a pulse E3 isapplied to the control circuitry, the switches SW8 and SW16 aresimultaneously closed as indicated at 51 in FIG. 2 so that any priorintegrated signals E14 and E38 which may be present will be immediatelydischarged to zero, the complete discharging being indicated at 52 inFIG.

2, following which the switches SW8 and SW16 are then opened. Also,following such complete discharge of the integrators the switches SW7and SW15 are simultaneously closed as indicated at 53 in FIG. 2 to startthe integration of the reference signal El (which may be processed asindicated at E12) and the information signal E2 (which may be processedas indicated at E36). The integration proceeds as illustrated by thesloping curves E14 and E38 in FIG. 2 until such time as the value of theintegrated signal EM reaches the value of the comparator voltage inputE25 as indicated at 54 in FIG. 2. Where the voltage source applied tothe terminal is a DC voltage, the discharge circuits R2, SW9 and R4,SW17 need not be utilized and, here, the voltage comparator 35 may thenproduce a signal for opening the switches SW7 and SW15 for stopping theintegration, and the integrated information signal E38 at time 54 inFIG. 2 will represent the integrated value of the information signal E2during such predetermined time interval and may be measured at output Ain FIG. l, the signal being a DC signal and being held by theinformation channel integrator just as the integrated signal E14 is heldby the reference channel integrator. In the event that there are nounwanted variations in the voltage supply to terminal 50, theintegrations will be completed precisely within the desiredpredetermined time interval between 53 and 54 as indicated in FIG. 2.

However, unwanted variations in the voltage supply may have an effectupon the integrations of the signals and if there should be increases inthe voltage, the slopes of the integrating curves E14 and E38 willincrease and the integrations will be terminated before the precise timeindicated at 54 in FIG. 2, and upon decrease in the voltage, the slopesof the integrating curves E14 and E38 will be decreased and theintegrations will be terminated after the precise time indicated at 54in FIG. 2. Thus, accurate time integrations of the reference andinformation signals are obtained and variations in the supply voltageare automatically compensated for. This is true where the voltage supplyis DC or in cyclic wave form, such as AC or the like.

Where the voltage supply to terminal 50 is in cyclic wave form, such asAC or the like, the, integrations of the reference signal E1 and theinformation signal E2 are simultaneously begun at the start of a firsthalf-cycle of the reference signal E1. In this respect, followingdischarge of the previous integrated reference and information signalsE14 and E38, as expressed above and as indicated at 51 and 52 in FIG. 2,the switches SW7 and SW15 are simultaneously closed at the start of afirst half-cycle of the reference signal E1 so that the processedreference and information signals E12 and E36 begin to be integrated asindicated at 53 in FIG. 2. The simultaneous integration continues alongthe sloping curves E14 and E38 until the integrated reference signal E14reaches a value corresponding to the value of the comparator voltageinput signal E25 as indicated at 54 in FIG. 2 and as described above toprovide accurate integrations of the reference and information signalsover the time interval between 53 and 54.

However, here, when this occurs the voltage comparator 35 produces asignal which is made available for the purpose of opening switches SW7and SW15 but which does not then do so. As a result, the integrationscontinue beyond time 54 as illustrated in FIG. 2. However, at the startof the next first halfcycle of the reference signal E1, the voltagecomparator signal becomes effective to open simultaneously the switchesSW7 and SW15 to stop the integrations as indicated at 55 in FIG. 2. Thissynchronizing operation is not illustrated in the simplified diagram ofFIG. 1, but this operation is detailed below in reference to theoperation of the computer illustrated in FIGS. 8A and 88. At the sametime, the voltage comparator signal becomes effective to closesimultaneously the switches SW9 and SW17 of the discharge circuits ofthe reference channel integrator and the information channel integratorto simultaneously partially discharge the integrators through theirrespective resistances R2 and R4 (which are equal to each other) untilthe integrated reference signal E14 discharges or returns to the valueof the voltage comparator input signal E25 as indicated at 56 in FIG. 2;When this occurs, the voltage held and retained at their then DC voltagevalues;

As a result, the cyclic wave signals E1 and E2 were integrated over atleast the desired predetermined time interval (53-54 in FIG. 2) whichwas corrected to eliminate unwanted variations in the voltage supply,and an integral number of cycles of the cyclic wave signals wereintegrated by extending the integration time interval (54-55 in FIG. 2).Both integrators integrated correctly (from 53 to 55 in FIG. 2) over atime interval which included an integral number of cycles of thereference signal input El. However, both integrated signals E14 and E38had a magnitude error at position 55 in FIG. 2, they having beenmultiplied by the factor T(5354) T(54-55) T(5354) stants R2.C1 and R4.C2are equal, both capacitors C1 and C2 discharged at the same rate, i.e.,the ratio of E38 to E14 remained constant. In other words, bothintegrated signals E14 and E38 (at 55 in FIG. 2) were rnultipliedhetween55 and T (53 '54 56 in FIG. 2) by the factor and are now correct.Accordingly, where the information signal E2 is a function of thereference signal E1, the computer of this invention will normalize theintegrated information output signal E38 to a precise time interval andwill provide an accurate time integration signal of the informationSince the time consignal E2 for an integral number of cycles for suchprecise time interval.

FIG. 3 illustrates a simplified electrical network particularly suitablefor computing cyclic wave trains, such as, for example, sinusoidal ACwave trains. Here, a source 60 of sinusoidal AC voltage is applied toone end of the primary 62 of a current transformer 61 having a secondary63. A resistance R9 is connected across the secondary 63 and one end ofthe secondary 63 is grounded. The other end of the secondary 63 providesa reference signal E1 which is sinusoidal and is proportional to the ACcurrent flow through the, primary winding 62, it being dependent uponthe turns ratio of the transformer 61 and the value of the resistance R9which may be constant for a desired scaling. The other end of theprimary 62 is connected through an unknown impedance Z to ground. Theunknown impedance Z may be substantially any electrical devicewhosepower and vector components are to be measured and computed. Thejuncture of the transformer primary 62 and the impedance 2 produces aninformation signal E2 which is dependent upon the electricalcharacteristics of the impedance Z.

, tegrated reference and information signals E14 and E18 are 5 Thecomputer diagrammatically illustrated in FIGS. 8A, 8B

may be associated with the network of FIG. 3 for computing the variouspower and vector components with respect to the impedance Z of FIG. 3,as for example, the voltage magnitude, the in phase component of thevoltage, the quadrature component of the voltage, the impedancemagnitude, the series resistance component of the impedance, the seriesreactance component of the impedance, the volt'ampere power (i.e., thevector or apparent power), the real power, the reactive power, the powerfactor, and the phase angle between the voltage and current.

Referring now to FIGS. 8A, 8B, which when laid side by sidediagrammatically illustrate the preferred computer of this inventionwhich includes a reference input tenninal for 1. providing a referenceinput signal Elwhich may be obtained from FIG. 3. It also includes aninformation signal input terminal for providing an information inputsignal E2 which may be obtained from FIG. 3. It further includes anexternal pulse input terminal for providing a pulse signal E3 forcontrolling the control circuitry of the computer. A variable pulsesignal E4 may be provided by a variable pulse generator 37 and a signalE5 which is 90 out of phase with the reference input signal E1 may beprovided by a 90 phase shift network 36.

I The computer further includes a reference channel processing device orsynchronous d t s)! sa ke by de e line L". associated with the referenceinput signal E1 and an information channel processing device orsynchronous detector, en-

closed by dotted lines 11, which is associated with the informationinput signal E2. In addition, the computer'includes a reference channelcomputer or integrator, enclosed by dotted lines 12, and an informationchannel computer or integrator, enclosed by dotted lines 13. Thecomputer further includes a timing and control system, enclosed bydotted lines 14.

Switches SW1, SW2, SW3 and SW4 are multiple position manual switcheswhich may be individually manually operated or they may be ganged, asdesired, switch SW1 having two positions, switch SW2 having threepositions, switch SW3 having three positions and switch SW4 having threepositions, the positions of the switches being indicated. The computeralso includes switches SW5 through SW17. These-switches are single polesingle throw switches which may be electromechanical, such as relays andthe like, or solid state such as transistor choppers and the like. Forpurposes of description, it is assumed that a positive voltage appliedto the controP input causes the switches to close (i.e., in & outterminals shorted) and that a-negative voltage causes the switches toopen (i.e., in & out terminals open). The reference channel integrator12 and the information channel integrator 13 respectively includeoperational amplifiers 15 and 16 which have low drift and both voltageand current gains of l0 or greater such that for all practical purposesthey may be considered infinite. The operational amplifiers l5 and 16have like operating and electrical characteristics. They alsorespectively include resistance R1 and capacitor C1 and resistance R3and capacitor C2, the resistances R1 and R3 being equal and thecapacitors C1 and C2 being equal. The control system 14 includes a pairof flipflops l7 and 18 which include a bistable circuit with two inputs.A pulse present at the on" input causes the output to assume the oncondition which remains until a pulse present at the o input causes theoutput to assume the ofi condition. Forpurposes of discussion a positiveoutput represents on, a negative output represents off. Flip-flops l7and 18 require positive going pulses at their inputs to cause operation,negative pulses being inefi'ecfive in causing operation.

The control system 14 further includes differentiators 19, 20 and 21whose outputs are a pulse corresponding in polarity and time to thetransitions of input square waves applied thereto. The computer furtherincludes inverters 22, 23, 24, 25, 26 and 27 which are linear amplifierswith a gain of -l (i.e., a phase inverter). The reference channeldetector and the information channel detector respectively includeadders 28 and 29. Each of these adders includes a circuit which providesan output proportional to the sum of its input signals and which alsoprovides for isolation of the input signals. For purposes of discussionthe gain in the adders is assumed to be +1. Adjustable gain amplifiers30 and 31 are associated respectively with the reference channeldetector and they constitute adjustable gain DC amplifiers with outputslinearly related to their inputs. The outputs are equal to K times theinpus. K is the gain and may be positive or negative with a valuedetermined by the desired scaling in the computer. The upper cutofifrequency should be high enough to allow a minimum of phase and gainvariation at the highest frequency of. interest,

, for example, 500 KHz.

Two squaring amplifiers 32 and 33 are also provided. These may comprisean overdriven amplifier or a Schrnitt trigger or the like whose outputis some fixed positive value for an input more positive than (v) andsome fixed negative value for an input more negative than (v), where (v)is some value which is for all values of input less than'the referenceinput. The

reference input is E25 which is provided by a reference input terminalB. This reference input E25 is normally a fixed negati'tie voltage.

The 90 phase shift network 36 referred to above provides an outputsignal E which is shifted 90 in phase to the input signal E1. Thevariable repetition rate pulse generator 37 referred to above produces avariable repetition rate pulse E4 arid may be manually or otherwisecontrolled.

{The computer also includes a gated peak detector 38 which may betypical peak detector whose output E40 is proportidnal to the peakamplitude of the input signal El without consideration, but, however,the output is prevented from changing except during the time that thegate input is positive. A detector whose output is proportional to theRMS or average value of the input signal El might also be used.Associated with the gated peak detector 38 is a multiplier-divider39"which is an analogue compu ftiln g device whose output B41 is :equalto a constant times I The multiplier-di- E40 vider 39 may be like thatillustrated in FIG. 15. The computer further includes a V bias terminaland an information output signal terminal A.

The various computations which may be made by the computer of FIGS. 8A,8B, forexample from the network of FIGS. 3, inay be set up bymanipulation of the manual switches SW1 to SW4. The following tabulationsets forth the switch positiohs and the connections made thereby and theformulae for such computations. In the formulae, A is the output signalE38; B is 1 for a fixed comparator reference voltage E25, but may haveany value when externally varied; K is a constant, determined by thedesired scaling required and it may be positive or negative; E1 is thereference input signal used for amplitude, phase,,frequency or timingcontrol; E2 is the infonnatioii signal input which is a function of E1in amplitude, phase oizfrequency; I is the phase angle between E1 andE2; and D is a constant and equals 90 for descriptive purposes.

(.1) V. (voltage magnitude) A=KBE2 SW1-1; SW2-3 (132-33); SW3-2 (E231);SW4-2 (E15-30).

(2) V cos 5 (in phase component of V) A=KBE2 cos. SW1-1; SW2-1 (El-33);SW3-2 (E2-31); SW4-2 (E15-30).

('3) V sin (quadrature component of V) A=KBE2 sin SW1-1; SW2-2 (E5-33);SW3=2 (E2-31); SW4-2 (E15-30). E2

(4) Z (impedance magnitude) A=KB E SW1-1;

SW2-3 (E2-33); SW3-2 (E2-31); SW4-1 (El-30). (5) R (series resistancecomponent of Z) A=KB -2 SW1-1; SW2-1 (El-33); SW3-2 (E2-31); SW4-1(El-30).

(6) X (series reactance component of Z) A=KB SW1-1; SW2-2 (E5-33); SW3-2(E2-31);

sw4-1 (El-30).

Several specific examples of the operation of the preferred form of thecomputer of this invention are set forth hereafter. First, reference ismade to FIGS. 8A, 8B and to the curves of FIGS. 9 and 10 where theswitches SW1 through SW4 are set for the computation of the seriesresistance component of the impedance Z of FIG. 3, computation (5)above, switch SW1 being in position 1, switch SW2 being in position 1,switch SW3 being in position 2, and switch SW4 being in position 1.Reference signal input E1 is therefore connected to the adjustable gainamplifier 30 and to both squaring amplifiers 32 and 33, and informationsignal input E2 is connected to adjustable gain amplifier 31. Referencesignal input E1 (FIG. 9)-

is assumed to be a sinusoidal sine wave and information signal input E2(FIG. 9) to bea sinusoidal sine wave lagging reference signal E1 by aphase angle 1 of Signal E5 (which is not used in this computation) is asinusoidal sine wave leading the reference signal E1 by a phase angle Dof 90.

With both signal inputs El and E2 applied, a trigger pulse E3 (FIG. 9)is applied at 51 (or E4 if switch SW1 is in position 2) and it operatesthe multivibrator 34 to its on state for producing a positive signal E14(FIG. 9) for a time interval which is longer than a half-cycle of thereference input signal E1. This signal E18 closes switches SW8 and SW16over such time interval to completely discharge the capacitors C1 and C2to zero for causing any previous integrated reference signal output E14and informafion signal output E38 to be discharged to and return tozero. By the end of such time interval the capacitors C1 and C2 arecompletely discharged and at the end of such time interval at 52controlled by the multivibrator 34 signal E18 returns to its off state(negative output) and causes switches SW8 and SW16 to open. Also, at thenegative going transition of E18, inverter 24 and differentiator 20cause a positive pulse to be generated at 1519 which in turn causesflip-flop 17 to change to its on state to provide a positive signal E20for closing switch SW1 1.

The reference input signal E1 is amplified by the'adjustable gainamplifier 30 and im output E7 is applied to the input of switch SW5 andto the inverter 22 and the output E8 of the inverter 22 is applied tothe input of switch SW6. With switch SW4 in position 1, as it here is,signal E7 is the same as signal E1 except for amplitude. (With switchSW4 in position 2, signal E7 is the same as signal E15 except foramplitude). Signal E8 to the input of switch SW6 is the same as signalE7 except that it has an 1 80 phase inversion.

Reference signal input E1 is also applied to the squaring amplifier 32and to squaring amplifier 33 when switch SW2 is in position 1 and theoutputs E15 and E28 therefrom are square wave signals and are positivewhen signal input E1 is positive and negative when signal E1 is negative(FIG. 9). Signal E15 is applied directly to the control terminal ofswitch SW5 and to inverter 23. Output signal E16 of inverter 23 is asquare wave signal like signal E15 but out of phase therewith and isapplied directly to the control terminal of switch SW6. The outputsignal E28 is a square wave signal and is the same as signal E15 and itis applied directly to the conn'ol terminal of switch SW13 and to theinverter 25. The output signal E29 from the inverter 29 is also a squarewave signal which is 180 out of phase with respect to signal E28 and itis applied to the control terminal of switch SW14.

Signal E9 from switch SW5 is identical to signal E7 during the time thatsquare wave signal E15 is positive and is zero when signal E15 isnegative. Signal E10 from switch SW6 is identical to signal E8 duringthe time that square wave signal E16 is positive and iszero when signalE16 is negative. Signals signal E2 exceptforamplitude. Signal E32 toswitch SW14 is is a square wave signal which is the same in phase assquare R wave signal E15, signal E28 being applied to inverter 25 and tothe control terminal of switch SW13, signal E29 being the same as signalE28 except that it has an 180 phase inversion. Signal E33 (FIG. fromswitch SW13 is identical to signal E31 during the time that square wavesignal B28 is positive and is zero when signal E28 is negative. SignalE34 (FIG.

. 10) from switch SW14 is identical to signal E32 during the time thatsquare wave signal E29 is positive and is zero when signal E29 isnegative. Signals E33 and E34 are applied to the adder 29 and the outputsignal E35 (FIG. 10) from the adder is the sum of signals E33 and E34,signal E35 being applied to switch SW15.

Square wave signal E is also applied to difl'erentiator 19 whose outputsignal E17 (FIG. 9) is positive and negative pulses at the respectivetransitions of signal E15. As expressed on toproduce a positive signalpulse E for closing switch SW11. The first positive pulse E17, whileswitch SW11 is so closed, is transmitted through switch SW11 to providea positive pulse E22 for switching flip-flop 18 to its on state. Theoutput signal E23 I from flip-flop 18 is differentiated bydifferentiator 21 to provide a positive pulse signal E24 for turning ofiflip-flop 17 which causes switch SW1] to switch off and thereby preventflip-flop 18 fromv again being turned on until a another trigger pulseE3 or E4 has occurred. The output signal 1523 from flip-flop 18 alsosimultaneously closes switches SW7 and SW15 for applying the processedsignals E11 and E35 to the reference channel and information channelintegrators 12 and 13 as indicated at E12 and E36 in FIGS. 9 and 10.

{The referencechanhel integrator 12 includes a resistance R1 receivingsignal E12 and providing signal E13 on one side or; capacitor C1 and anoperational amplifier 15 which in produce a time integrated signal E14on the other side th reof. Likewise, the information channel integratorincludes a resistance R3 receiving signal E36 and providing signal E37onfone side of a capacitor C2 and an operational amplifier 16 which inturn produce a time integrated signal E38 on the other side thereof. Theresistances R1 and R3 are equal, the

capacitances C1 and C2 are equal, and the electrical characteristics ofthe operational amplifiers 15 and 16 are equal. As expressed above,switches SW8 and SW16 are for the purpose of co rnpletely dischargingthe integrators when closed, also,

resistance R2 and switch SW9 and resistance R4 and switch SW17 are forthe purpose of partially discharging the integratorts, the resistancesR2 and R4 being equal.

When switch SW7 is closed as aforesaid, the integration of signal B12 isstarted at 53 and the integration time is controlled by the timeconstant Rl C1. When the integrated output, signal E14 (FIG. 9) becomesequal at 54 to the comparatorjf voltage input E (FIG. 9), the voltagecomparator 35 responding to such signals changes its output signal E26(FIG. 9)Ilfrom negative to positive. output signal E26 thus goespositive, switch SW10 is closed. The next positive going pulse E17 fromthe differentiator 19 is then transmitted through SW10 at E21 to causeflip-flop 18 to turn off and change signal E23 (FIG. 9) from positive tonegative, at which time 55, switches SW7 and SW15 are sirriiiltaneouslyopened to stop the integration. During the timeinterval that flip-flop18 was on between 53 and 55 the infer-mation integrator 13 wasintegrating signal E36 with an integration time constant R3 C2 forinformation signal E38.

At this time 55 both integrators have integrated their respective inputsignals E12 and E36 for a time of T(5354)+ T( 54-5S). T(5354) is thedesigned integrating time intervalgstarting at the first positive goingtransition of reference producing the integrated 1 signal El and endingat the instant that integrated reference E14 equalled comparatorreference voltage signal E25.

When the voltage comparator Both integrators continued to integrate,however, for an additional time interval T(54-55) which is the timerequired for the first positive going transition of reference signal E1after T(5354). Both integrators have integrated correctly over timeperiods which are an integral number of cycles of the goes negative at55 asdescribed above, inverter 27 produces a positive signal which isapplied to the control terminal of switch SW12 to close the same. SwitchSW12 thereupon applies the positive signal E26 from the voltagecomparator 35 to the negative bias signal E27 which overrides the sameand causes the same to become positive for closing switches SW9 andSW17. Closure of switches SW9 and SW17 partially discharges theintegrators 12 and 13 through resistances R2 and R4 respectively. Thetime constants R2 C1 and R4 C2 are equal and, therefore,,both capacitorsC1 and C2 discharge at the same rate, i.e., the ratio of integratedsignals E38 and E14 remains constant.

When the integrated reference signal E14 is discharged to and becomesgreater than the comparator reference voltage signal input E25, thevoltage comparator signal E26 becomes negative which in turn causessignal E27 to again become negative at 56 for opening switches SW9 andSW17 to stop the partial discharge of capacitors Cl and C2 at 56. Sinceboth of the integrated .output signals E14 and E38 have been dischargeduntil signal E14'becornes equal to thecomparator voltage input signalE25, then both signalsli14 and E38 have T (53-54) been multrphed by thefactor MW QQQLIZ 5 7 and are now correct. Accordingly, where theinformation signal E2 is a function of the reference signal E1, theintegrated information output signal E38 is normalized to a precise timeinterval (53-54) and will provide an accurate time integration signal ofthe information signal E2 for an integral number of cycles thereof andregardless of voltage variations afiecting input signals El and E2.

Since it was assumed above that the information signal input E2 laggedthe reference signal input E1 by the corrected information signal E36(FIG. 10) applied to the information channel integrator 13 wassymmetrical about zero and, hence, the integrated signal E38. (FIG. 10)remained at zero, indicating that R, the series resistance component ofthe impedance ZofFIG.3, (A=KB E25? When the computer afiiianfiinafi isset if; for computing X, computation (6) above, the series reactancecomponent of z of FIG. 3 (A=KB switch SW1 is in'position 1, switchSW2 isin position 2 to connect the 90 phase shift network to the squaringamplifier 33,

) was zero.

switch SW3 is in position 2 to connect information signal E2 i to theadjustable gain amplifier 31, and switch SW4 is in position 1 to connectreference signal E1 to the adjustable gain amplifier 30. Under theseconditions the various signals pertaining to the reference channel arethe same as those discussed above and illustrated in FIG. 9. FIG. 11represents the significant signals for the information channel for theseconditions. The square wave signal E28 from the squaring am- E34 and E33are added by adder 29 to provide signal E35 and to provide a signal E36to be integrated by the information channel integrator 13. Theintegrated information signal E38 following integration shows asubstantial series reactance component of the impedance Z.

' When the computer is set up for computing 2, computation (4) above,the impedance magnitude of Z of FIG. 3

E2 (A-Jtb E1 switch SW1 is in position 1, switch SW2 is in position 3 toconnect infonnation signal E2 to the squaring amplifier 33, switch SW3is in position 2 to connect information signal E2 to the adjustable gainamplifier 31, and switch SW4 is in position 1 to connect the referencesignal E1 to the adjustable gain amplifier 30. Under these conditions,the various signals pertaining to the reference channel are the same asthose discussed above and illustrated in FIG. 9. FIG. 12 represents thesignificant signals for the information channel for these conditions.The square wave signal E28 from the squaring amplifier 33 is in phasewith the information signal E2 and lags signal E15 by 90 and it controlsswitches SW13 and SW14. When signal E28 is negative, signal B33 is zeroand when signal E28 is positive, signal E33 corresponds to the positivegoing portion of information signal E2. When signal E28 is negative,signal E34 corresponds to the inversion of negative going portion ofinformation signal E2 and when signal E28 is positive, signal E34 iszero. These signals E33 and E34 are added by adder 29 to provide asignal E36 to be integrated by the information channel integrator 13.The integrated information signal E38 following integration shows asubstantial impedance magnitude of the impedance Z.

When the computer is set up for computing cos D, computation above, thepower factor, with respect to the impedance Z of FIG. 3 (A=KB cos D),switch SW1 is in position 1, switch SW2 is in position 3 for connectinginformation input signal E2 to the squaring amplifier 33, switch SW3 isin position 3 for connecting reference input sigial E1 to the adjustablegain amplifier 31, and switch SW4 is in position 1 for connecting thereference input signal E1 to the adjustable gain amplifier 31, andswitch SW4 is in position 1 for connecting the reference input signal E1to the adjustable gain amplifier 30. Under these conditions the varioussignals pertaining to the reference channel are the same as thosediscussed above and illustrated in FIG. 9. FIG. 13 represents thesigrificant signals for the information channel for these conditions.Switches SW13 and SW14 are controlled by the square wave signal E28 fromsquaring amplifier 33, like that of FIG. 12, which is in phase with theinformation signal input E2. When signal E28 is negative, signal E33 iszero and when signal E28 is positive, signal E33 corresponds to thereference signal El. When signal E28 is negative, signal E34 correspondsto the inversion of the reference signal E1 and when signal B28 ispositive, signal E34 is zero. These signals E33 and E34 are added byadder 29 to provide signal E35 to provide signal E36 to be integrated bythe information channel integrator 13. The processed infonnation signalE36 is symmetrical about zero and, hence, the integrated signal E38remains at zero, indicat' ing that the power factor (cos 1 is zero.

When the computer is set up for computing 51 computation (ll) above, thephase angle between the voltage and current, with respect to theimpedance Z to FIG. 3 (A=KB (D+ l switch SW1 is in position 1, switchSW2 is in position 3 to connect the information signal E2 to thesquaring amplifier 33, switch SW3 is in position 1 to connect thesquaring amplifier 32 through E to the adjustable gain amplifier 31, andswitch SW4 is in position 2 to connect the squaring amplifier 32 throughE15 to the adjustable gain amplifier 30. FIG. 14 represents thesignificant signals pertaining to the reference and information channelsfor these conditions. Signal E7 from the adjustable gain amplifier 30 isa square wave signal which is the same as square wave signal E15 exceptfor amplitude, and signal E8 from the inverter 22 is the same as signalE7 except for an 180 phase inversion. Signals E9 and E10 (FIG.

14) are added by adder 28 to produce signal E11 which is gated at E12during the positive pulse E23 to produce the integrated reference signalE14. Square wave signal E28 from squaring amplifier 33 is in phase withthe information signal input E2. Signal E31 from the adjustable gainamplifier-31 is a square wave signal which is the same as signal E15except for amplitude, and signal E32 from inverter 26 is the same assignal E31 except for an 180 phase inversion. Signals E33 and E34 areadded by adder 29 to produce signal E35 which is gated at E36 during thepositive pulse E23 to produce the iii-- tegrated information signal E38.Since signal E36 is symmetrical about zero, the integration product iszero which indicates that I the phase angle, is the assumption made inconnection with the above computations.

Several specific examples, utilizing the curves of FIGS. 9 to 14, forperforming the computations of items (4), (5), (6), l0) and l 1) of theabove tabulation have been considered in detail for providing a thoroughunderstanding of this invention. It is not considered necessary tofurther consider in detail the other items of said tabulation other thanto note the switch positions and connections made thereby as set forthin the tabulation, the versatility of the computer of this inventionbeing readily apparent from the foregoing description.

If signals E20 from the flip-flop 17 and E26 from the voltage comparator35 are differentiated and connected to replace the signals E21 and E22respectively to the flip-flop 18 (differentiator 19 and switches SW10and SW11 being eliminated) the computer will accept and compute DC orpulse input signals.

The network of FIG. 4 is like that of FIG. 3 except that the signaloutputs E1 and E2 thereof are reversed for connecting the same to thecomputer of FIGS. 8A, 8B. As a result the computer computes the Y oradmittance components of the unknown admittance Y under test and, also,current components using voltage as a phase reference by suitablemanipulation of the switches SW1 and SW4. The following is a tabulationincluding the switch positions and connections and formulae for suchcomputations.

15 Y (admittance magnitude) A=KB SW1-1;

SW2-3 (E233); SW32 (E231); SW41 (E130).

(16) G (parallel resistance component of Y) A=KB E2 cos E1 SW1-4; SW2-1(El-33); SW3-2 122-31 SW4-1 (E130).

(17 B (parallel reactive component of Y) A=KB SW1-1; SW2-2 (E5-33) SW3-2(E2-31); SW4-l (El-30).

(18) Cos (power factor) A=KB cos SW1-1; SW2-3 (E2-33); SW3-3 (EL-31);SW4-1 (El-30).

(19) (phase angle between V & I) A=KB (D+) SW11; SW2-3 (E2-33); SW3-1(E15-31); SW4-2 (E15-30) In the light of the foregoing explanations, itis not believed necessary to describe in more detail the operation ofthe computer of FIGS. 8A, 8B in conjunction with the network of FIG. 4.

FIG. 5 illustrates a network for direct measurement of the transferfunctions of a device under test 64, labeled D.U.T., signal E1 being thereference signal and signal E2 being the information signal, and signalsE1 and E2 being applied to the computer of FIGS. 8A, 8B. Thecomputations here involved are based on the formula A: K1 K2 E2 and E1are functions of frequency, K1 is the nominal loss or gain of the device64 under test, K2 is the scaling factor of where tegrated informationsignal B38 is a measure of the frequency response. To compute the phaseresponse where the phase angle I is a function of frequency, switch SW1is in position 1, switch SW2 isin position 3 to connect E2 to 33, switchSW3 is in'position l to connect E to 31, and switch SW4 is in position 2to connect E15 to 30. The integrated information signal B38 is a measureof the phase angle D.

1 FIG. 6 illustrates a system for making comparison measurements oftransfer functions, such as, comparison measurements of transferfunctions, such as, comparison measurements between standard and testacoustic receivers or other transducers. Here, an: AC voltage source 60operates an acoustic transmitter 65 for transmitting acoustic waves to astandard acoustic receiver 67 and an unknown or test acoustic receiver68. The standard receiver 67. provides a reference 7 signal E1 and thetest receiver 68 provides an information signal E2, the signals El andE2 being applied to the computer of FIGS. 8A, 8B. The system alsopreferably includes a potentiometer 69 for adjusting the comparatorvoltage signal E25 applied to the terminal B of FIG. 8B.

The computation for the relative frequency response of the 7' where E2and E1 are functions offrequency, K1 is the nominal scaling factorbetween E2 and E1, K2 is the scaling factor of the computer includingthe comparator voltage B times a constant, B is a fixed voltage whichmay be externally controlled, and A is the information-output signal 38of the computer. To compute the relative frequency response, switch SW1is in position 1, switch SW2 is in position 3 to connect E2to 33, switchSW3 isin position 2 to connect E2 to 31 and switch SW4 is in position 1to connect E1 to 30. The integrated information signal E38 provides ameasurement of the relative frequency response.

The computation of the absolute frequency response of the test receiver68, provided the acoustic intensity of the waves 66'js maintainedconstant at both receivers 67 and 68, involves the formula A=K1 K2 E2,where E2 is a function of frequency, and 13 included in K2 is fixedvoltage. Here, switch SW1 is in positionl, switch SW2 is in position 3to connect E2 to33, switch SW3 is in position 3 to connect 39 to 30. Theintegrated information signal E38 provides a measurement of the absolutefrequency response. Wherethe-intensity of the acoustic waves 66 cannotbe maintained constant at the receivers 67 and 68, the comparatorreference voltage source B (E25) can be varied, as by the potentiometer69, proportionally to the known response of the standard receiver 68. Acurve follower or similar device may be used for automatic adjustment ofthe voltage B(E25 or it may be adjusted manually in discrete steps sothat voltage B(E25) is made to correspond to the normalized referencesignal input E1, i.e., to the known response of a standard receiver.

FIG. 7 discloses a network for power measurements of a device under testwherein the sine wave signals are of high distortion and/or have highharmonic components. Here, a source of alternating current 60 isconnected to one end of the primary 62 of a current transformer 61having a secondary 63, the other end of the primary 62 being connectedthrough the device under test 70, labeled D.U.T.', to ground. Thecurrent source 60 directly provides the reference signal input E1 whichis utilized only for timing purposes. A resistance R9 is connectedacross the secondary 63 of the transformer 61, one end of the resistanceR9 being connected to ground and the other end thereof being connectedto the input of an amplifier 71Q'l'he output of the amplifier 71 isconnected to ground through a winding 72 of a Hall effect device 73.Reference signal E1 .is applied to the Hall effect device 73, labeled H.E.D., which also is grounded. The signal outputs of the Hall receivers67 and 68 is based on the formula A: K1 K2 effect device are connectedto the inputs of a differential amplifier 74 and the output of thedifferential amplifier 74 provides information signal E2. Reference andinformation signals El and E2 are applied to the computer of FIGS. 8A,8B.

Signal E2==CVI (in instantaneous values where v is the signal voltageand I is the current in the primary circuit, and where C is a scalingfactor and is constant. Thus, in computing the power measurement A=K1-.J F2 dt. other words, A=KB times the integra tli1e instantaneous powerover the time interval 0 to T, ",or A=KB times the average power overinterval 0 to T. In this computation switch SW1 is in position 1, switchSW2 is in position 3 to connect E2 to33, switch SW3. is in position2 toconnect E2 to El; and- 1 switch SW4 is in position 2 to connect E15 to30. The integrated reference signal E38 or A following the integrationis a measure of the average instantaneous power over the integrationinterval. If the squaring amplifier 33 is disabledsu ch that its outputE28 is either on or off, the average power is measured.

By adding additional information channels including processing device 11and integrating device 13, as illustrated in broken linesin FlGS. 8A and8B, :along with appropriate control connections thereto, computations ofa multiplicity of functions of the information signal E2 may besimultaneously performed. Also, by varying the value of the comparatorvolt age input signal Ell multiplication and division computations mayalso be provided.

,fThe computer shown in block diagram in FIGS. 8A, 8B is Pai'ticularlyadap b for computing the Parameters trical or electronic networks andelectromechanical devices and systems in the audio frequency range from10.0 Hz. to 500 Hz., because of the commercial importance of parametermeasurements in this frequency range and the readily availableelectronic circuit building blocks for this frequency range frommanufactures which are more or less off the shelf. In addition tomeasurement of steady DC or pulses or slowly varying AC by making theabove-described revisions to the computer, measurements in the megacyclefrequency range and above may also be made. in accordance with thisinvention, but this would requiremore sophisticated electronic circuitbuilding blocks which are not normally ofl the shelf" items.

FIG. 15 diagrammatically illustrates another form of a computerproviding a simple approach of a multiplier-divider suitable for usewhere two inputs E40 and F are limited in range and have the samepolarity. The third input E15 may have any value or polarity or maybe cyclie. 'l 'he mathematical 0 tion erforrned is I C pera p s C E4 tivewhen signal B84 is greater than signal E and negative when signal B84 isless than signal E85. Switches SW81 and SW82 are closed (shortcircuit)when signal E86 is positive and are open (open circuit) when signal E86is negative. One end of a resistance R15 is connected to the signal,input,.E40 and the other end thereof is connected to ground throughcapacitor C11, to ground through resistance R16 and switch SW81, and tothe voltage comparator 83 at E84. One endof a resistance Rl7 isconnected to the signal input E15 and the other end thereof is connectedto ground through capacitor C12, to ground through resistance R18 andswitch SW82, and to the signal output terminal C at E41. The ratio ofresistance R15 to resistance R16 is equal to the ratio of resistance R17to resistance R18 and the product (R15) (C11) is equal to the product(R17 (C12). Signal E40 is always greater than signal E85. Signals E40and E85 are DC or slowly varying and only for descriptive purposesherein are always positive. The ratio of resistance R15 to resistanceR16 is established such that at steady state with switch SW81 closedsignal E84 is always less than signal E85 with signal E40 at itsdesigned maximum value.

The operation of the computer of FIG. 15 is illustrated by the curves ofFIG. 16. For providing a division computation signal E85 is fixed at adesired value. Switches SW81 and SW82 have previously been closed todischarge the capacitors C11 and C 12 to bring the signals E84 and E41to zero and to make signal E86 negative. The switches SW81 and SW82 werethen opened and were held open by the negative signal E86. At time 90signals E40 and E15 are simultaneously applied and capacitor C11 chargestoward signal E40 through resistance R15 (signal E84) and capacitor C12charges toward signal E15 through resistance R17 (signal E41). Whensignal E84 becomes greater than signal E85 at time 91, the voltagecomparator 83 operates to make its output signal E86 positive. Note thata small delay in the operation of the voltage comparator 83 has beenshown to clarify the operation of the computer. When the voltagecomparator output signal E86 thus becomes positive, the switches SW81and SW82 are simultaneously closed to simultaneously discharge thecapacitors C11 and C12 through resistances R16 and R18, respectively,(signals E84 and E41). Whensignal E84 becomes less than signal E85 attime 92, the voltage comparator 83 causes signal E86 to again becomenegative to again cause switches 81 and 82 simultaneously to open,whereupon capacitors C11 and C12 begin again to charge. The dischargeand charge cycles repeat continuously thereafter. The average value ofthe output C (sign al E4 1) therefore has a value of (E15) (F) Em, whereF 18 fixed. This cor responds to division.

Alternately, signal E40 may be fixed with F (signal E85) variable. Here,the avergg valueof theoutput C (signal E41) hasavalue 01' C average:(E15) (Eg wlfiri'eilll is fixed. This corresponds to multiplication. Bysimultaneously or progressively varying signal E40 and signal E85 (F)both multiplication and division may be accomplished.

The input signal E40 may be considered a reference signal and the inputsignal E15 may be considered an information signal, both of which aretime integrated until the integrated reference signal E84 reaches thecomparator voltage signal E85, with the result that the time integratedinformation signal represents the multiplication or divisioncomputation.

If signal E15 is a cyclic wave signal, such as a square wave signalillustrated in FIG. 17, and the time constants are adjusted to be lessthan the half-cycle periods of signal E15, such a cyclic wave signal maybe multiplied or divided as shown in FIG. 17, curve E15 being the squarewave input signal and curve E41 being the C average output signal foreach halfcycle of the input signal. This particular arrangement usingthe square wave input signal E15 is admirably suitable for themultiplier-divider 39 of the computer of FIG. 8A. There, the voltagecomparator input signal F(signal E85)-is an internal adjustment.

By adding additional information channels as indicated by block 95 inFIG. 15 with appropriate control connections thereto, multiplication anddivision of other additional functions may be simultaneously performed.While for purposes of illustration several forms of this invention havebeen disclosed, other forms thereof may become apparent to those skilledin the art upon reference to this disclosure and, therefore, thisinvention is to be limited only by the scope of the appended claims.

I claim:

1. A computing method comprising the steps of providing a referencecyclic wave signal having amplitude, phase and frequency components,providing an information cyclic wave signal having amplitude, phase andfrequency components which are functions of those of the referencecyclic wave signal, processing said cyclic wave signals to provideprocessed reference and infonnation signals, simultaneously startingintegration with respect to time of both of said processed signals atthe start of a half-cycle of the reference cyclic wave signal forproducing time integrated reference and information signals,simultaneously continuing such time integration of said processedsignals until the time integ'ated reference signal reaches at least apredetermined value, and then at the start of an ensuing half-cycle ofthe reference cyclic wave signal simultaneously discontinuing suchintegrations of said processed signals and simultaneouslyproportionately decreasing the values of the time integrated referenceand information signals until the time integrated reference signalreturns to said predetermined value, whereby the time integratedinformation signal indicates the time integal of the processedinformation signal over an integral number of half-cycles of thereference cyclic wave signal.

2. A computing method as set forth in claim 1 wherein the simultaneousstarting of the integrations of both of said processed signals takeplace at the start of a first half-cycle of the reference cyclic wavesignal, and wherein the simultaneous discontinuation of the integrationsof the processed signals and the simultaneous proportionate decrease ofthe time integrated reference and information signals take place at thestart of the first half-cycle of the reference cyclic wave signal afterthe time integrated reference signal reaches said predetermined value,wherebythe time Etegra ted information signal indicates the timeintegral of the processed information signal over an integral number offull cycles of the reference cyclic wave signal.

3. A computing method as defined in claim 1 wherein the processing ofthe cyclic wave signals comprises the steps of inverting botln of saidcyclic wave signals during the second-half cycles to provide theprocessed reference and information signals.

4. A computing method as defined in claim 2 wherein the processing ofthe cyclic wave sigials comprises the steps of inverting both of saidcyclic wave signals during the second-half cycles to provide theprocessed reference and information signals.

5. A computer comprising means for providing a reference signal, meansfor providing a comparator voltage input signal of predetermined value,a first computer device associated with the reference signal forcomputing the same and providing a computed reference signalcorresponding to the computation, a second computer device associatedwith the informa tion signal for computing the same and providing acomputed information signal corresponding to the computation, thecomputing characteristics of the second computer device corresponding tothose of the first computer device, switch means associated with thefirst and second computer devices and operable to a first condition forcausing simultaneous computations of said reference and informationsignals and to a second condition for simultaneously discontinuing saidcomputations, control means including means for operating said switchmeans to said first condition for simultaneously starting saidsimultaneous computations of said reference and information signals,said control means including a voltage comparator associated with saidcomparator voltage input signal and the computed reference signal of thefirst computer device and responsive to the computed reference signal ofthe first computer device reaching the comparator voltage input signalfor controlling the operation of said switch means to said secondcondition to terminate simultaneously the computations by both saidfirst and second computer devices, the computed infonnation signal ofthe second computer device indicating the desired computation of theinfonnation signal computed thereby.

6. A computer device as defined in claim 5 and including means foradjusting the value of the reference signal or the value of thecomparator voltage input signal for dividing or multiplying the computedinfonnation signal.

7. A computer as defined in claim wherein said first and second computerdevices are time integrators for providing time integrations of thereference and information signals.

8. A computer as defined in claim 6 wherein said first and secondcomputer devices are time integrators for providing time integrations ofthe reference and information signals.

9. A computer as defined in claim 5 wherein said first and secondcomputer devices are time integrators for providing time integrations ofthe reference and information signals for producing time integratedreference and information signals, wherein said comparator voltage inputsignal which is reached by the time integrated reference signaldetermines the desired time interval of said time integrations, andwherein the computed information signal indicates the time integral ofthe information signal over said desired time interval.

10. A computer as defined in claim 5 wherein said first and secondcomputer devices are time integrators for providing time integrations ofthe reference and information signals wherein the time integrationinterval is determined by the values of the reference signal and thecomparator voltage input signal which is reached by the time integratedreference signal, and wherein the computed information signal indicatesthe time integral of the information signal over such time interval.

11. A computer as defined in claim 10 and including means for adjustingthe value of the reference signal or the value of the comparator voltageinput signal for dividing or multiplying the time integrated informationsignal.

12. A computer comprising means for providing a reference cyclic wavesignal having amplitude, phase and frequency components, means forproviding an information cyclic wave signal having amplitude, phase andfrequency components which are functions of those of the referencecyclic wave signal, a first processing device associated with thereference signal and providing a processed reference signal, a secondprocessing device associated with the information signal and providing aprocessed information signal, a first integrator associated with theprocessed reference signal for integrating the same over a time intervalfor providing a time integrated DC reference signal, a second integratorassociated with the p ocessed information signal for integrating thesame over a time interval for providing a time integrated DC informationsignal, the integrating characteristics of said second integratorcorresponding to those of the first integrator, means for providing a DCcomparator voltage input signal of predetermined value, switch meansoperable when closed for connecting the processed reference andinformation signals respectively to the first and second integrators forsimultaneous time integrations of said processed signals, control meansincluding means responsive to the start of a half-cycle of the referencecyclic wave signal for closing said switch means for simultaneouslystarting said simultaneous time integrations of said processed referenceand information signals, said control means including a voltagecomparator associated with said DC voltage comparator input signal andthe time integrated reference signal of the first integrator andresponsive to the integrated DC reference signal reaching the DCcomparator voltage input signal value for producing a control signal butallowing continued integration by both the first and second integrators,a corresponding discharge circuit for each of said first and secondintegrators, said control means including means responsive to the startof a half-cycle of the reference cyclic wave signal following productionof said control signal for simultaneously opening said switch means toterminate simultaneously the time integrations by both of said first andsecond integrators and for simultaneously closing said correspondingdischarge circuits for simultaneously partially discharging both of saidintegrators therethrough, said control means including means responsiveto elimination of said control signal when said control signal iseliminated by the partial discharge of the integrated DC referencesignal of said first integrator to the DC comparator voltage: signalinput value for simultaneously opening said corresponding dischargecircuits to prevent further discharging of both of said first and secondintegrators therethrough, the time integrated DC information signal ofthe second integrator indicating the time integral of the processedinformation signal over an integral number of half-cycles of thereference cyclic wave signal.

13. A computer as defined in claim 112 wherein said means of saidcontrol means which closes said switch means is responsive to the startof a first half-cycle of the reference cyclic wave signal, and whereinsaid means of said control means which opens said switch means andcloses said corresiamiig discharge r neansis responsive to the start ofthe next ensuing first half-cycle of the reference cyclic wave signalfollowing production of said control signal, whereby the time integratedinformation signal indicates the time integral of the processedinformation signal over an integral number of full cycles of thereference cyclic wave signal.

14. A computer as defined in claim 12 wherein said first and secondprocessing devices include means for detecting the cyclic wave signalsand inverting the second half-cycles to provide the processed signals.

15. A computer as defined in claim 12 wherein said first and secondprocessing devices include means for detecting the cyclic wave signalsand inverting the second half-cycles to provide the processed signals.

16. A computer as defined in claim 5 wherein said means for providingthe reference signal and the related information signal comprise avoltage source, a circuit powered by the voltage source and including adevice under test, means coupledto the circuit and responsive to thevolta e source for providing the reference signal and means coup ed tothe eucuit and responsive to the device under test for providing therelated information signal.

17. A computer as defined in claim 12 wherein said means for providingthe reference signal and the related information signal comprise avoltage source, a circuit powered by the voltage source and including adevice under test, means coupled to the circuit and responsive to thevoltage source for providing the reference signal, and means coupled tothe circuit and responsive to the device under test for providing therelated information signal.

18. A computer as defined in claim 12 and including a source of energy,a standard transducer and a test transducer subjected to the energyproduced by said source, said standard transducer producing thereference signal and said test transducer producing the relatedinformation signal.

19. A computer as defined in claim 12 and also including an adjustablegain amplifier and a squaring amplifier for each of the first and secondprocessing devices, a phase shift device, and a plurality of switchesfor selectively interconnecting the reference signal, the informationsignal, the 90 phase shift device, and the squaring amplifier of thefirst processing device to the squaring amplifier of the secondprocessing device and the adjustable gain amplifiers of the first andsecond processing devices for desired vector component computations.

20. A computer as defined in claim 12 and also including an adjustablegain amplifier and a squaring amplifier for each of the first and secondprocessing devices, a 90 phase shift device, a multiplier-dividerdevice, and a plurality of switches for selectively interconnecting thereference signal, the information signal, the 90 phase shift device, andthe multiplier-divider device to the squaring amplifier of the secondprocessing device and the adjustable gain amplifiers of the first andsecond processing devices for desired power computations.

